1 tm features ? fast access time -v dd = 5v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450ns -v dd = 10v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250ns common data inputs and outputs multiple chip select inputs to simplify memory system expansion description the cdp1823 and cdp1823c are 128-word by 8-bit cmos sos static random-access memories. these memories are compatible with general-purpose microprocessors. the two memories are functionally identical. they differ in that the cdp1823 has a recommended operating voltage range of 4v to 10.5v, and the cdp1823c has a recommended oper- ating voltage range of 4v to 6.5v. the cdp1823 memory has 8 common data input and data output terminals for direct connection to a bidirectional data bus and is operated from a single voltage supply. five chip- select inputs are provided to simplify memory-system expan- sion. in order to enable the cdp1823, the chip-select inputs cs2 , cs3 and cs5 require a low input signal, and the chip- select inputs cs1 and cs4 require a high input signal. the mrd signal enables all 8 output drivers when in the low state and should be in a high state during a write cycle. after valid data appear at the output, the address inputs may be changed immediately. output data will be valid until either the mrd signal goes high, the device is deselected, or t aa (access time) after address changes. pinout ordering information 5v 10v package temp. range pkg. no. cdp1823ce cdp1823e pdip -40 o c to +85 o c e24.6 cdp1823cd cdp1823d sbdip -40 o c to +85 o c d24.6 cdp1823cdx - burn-in d24.6 cdp1823, cdp1823c (pdip, sbdip) top view 1 2 3 4 5 6 7 8 9 10 11 12 bus 0 bus 1 bus 2 bus 3 bus 4 bus 5 bus 6 bus 7 cs1 cs2 cs3 v ss 16 17 18 19 20 21 22 23 24 15 14 13 v dd ma1 ma2 ma3 ma4 ma6 mrd cs5 cs4 ma0 ma5 mwr march 1997 cdp1823, cdp1823c 128-word x 8-bit lsi static ram file number 1198.2 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a trademark of intersil americas inc. copyright ? intersil americas inc. 2002. all rights reserved
2 operational modes function mrd mwr cs1 cs2 cs3 cs4 cs5 bus terminal state read 0x10010storage state of addressed word write 1010010i nput high-impedance stand-by (active) 1110010high im pedance not selected xx0xxxxhigh im pedance x x x 1 x x x high impedance xxxx1xxhigh im pedance xxxxx0xhigh im pedance xxxxxx1high im pedance logic 1 = high, logic 0 = low, x = don?t care cdp1823, cdp1823c
3 absolute maximum ratings thermal information dc supply voltage range, (v dd ) (all voltages referenced to v ss terminal) cdp1823 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5v to +11v cdp1823c. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +7v input voltage range, all inputs . . . . . . . . . . . . . -0.5v to v dd +0.5v dc input current, any one input . . . . . . . . . . . . . . . . . . . . . . . . 10ma operating temperature range (t a ) package type d . . . . . . . . . . . . . . . . . . . . . . . . . -55 o c to +125 o c package type e . . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to +85 o c thermal resistance (typical) ja ( o c/w) jc ( o c/w) pdip package . . . . . . . . . . . . . . . . . . . 60 n/a sbdip package. . . . . . . . . . . . . . . . . . 60 17 maximum storage temperature range (t stg ) . . .-65 o c to +150 o c maximum junction temperature plastic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150 o c maximum lead temperature (during soldering) . . . . . . . . . . 300 o c recommended operating conditions at t a = full package temperature range. for maximum reliability, operating conditions should be selected so that operation is always within the following ranges: parameter limits units cdp1823d cdp1823cd min max min max supply voltage range 4 10.5 4 6.5 v recommended input voltage range v ss v dd v ss v dd v static electrical specifications at t a = -40 o c to +85 o c, except as noted: parameter symbol conditions limits units v o (v) v in (v) v dd (v) cdp1823 cdp1823c min (note 1) typ max min (note 1) typ max quiescent device current i dd - 0, 5 5 - - 500 - - 500 a - 0, 10 10 - - 1000 - - - a output low (sink) current i ol 0.4 0, 5 5 2 4 - 2 4 - ma 0.5 0, 10 10 4.5 9 - - - - ma output high (source) current i oh 4.6 0, 5 5 -1 -2 - -1 -2 - ma 9.5 0, 10 10 -2.2 -4.4 - - - - ma output voltage low-level v ol -0, 55 - 0 0.1 - 0 0.1v - 0, 10 10 - 0 0.1 - - - v output voltage high-level v oh -0, 554.9 5 - 4.9 5 - v - 0, 10 10 9.9 10 - - - - v input low voltage v il 0.5, 4.5 - 5 - - 1.5 - - 1.5 v 0.5, 9.5 - 10 - - 3 - - - v input high voltage v ih 0.5, 9.5 - 5 3.5 - - 3.5 - - v 0.5, 9.5 - 10 7 - - - - - v input leakage current i in any input 0, 5 5 - - 5- - 5 a 0, 10 10 - - 10 - - - a operating current (note 2) i dd1 -0, 55 - 4 8 - 4 8ma - 0, 10 10 - 8 16 - - - ma three-state output leakage current i out 0, 5 0, 5 5 - - 5- - 5 a 0, 10 0, 10 10 - - 10 - - - a input capacitance c in ----57.5-57.5pf output capacitance c out ----1015-1015pf notes: 1. typical values are for t a = +25 o c and nominal v dd . 2. outputs open circuited; cycle time = 1 s. cdp1823, cdp1823c
4 + dynamic electrical specifications at t a = -40 to +85 o c, v dd 5%, t r , t f = 20ns, c l = 100pf parameter symbol v dd (v) limits cdp1823 cdp1823c units (note 2) min (note 1) typ max (note 2) min (note 1) typ max read cycle (see figure 1) access time from address change t aa 5 - 275 450 - 275 450 ns 10 - 150 250 - - - ns access time from chip select t doa 5 - 150 250 - 150 250 ns 10 - 100 150 - - - ns mrd to output active t am 5 - 150 250 - 150 250 ns 10 - 100 150 - - - ns data hold time after read t doh 5 255075255075ns 10 15 25 40 - - - ns notes: 1. typical values are at t a = 25 o c and nominal voltage. 2. time required by a limit device to allow for the indicated function. address t aa t am t doa t doh mrd cs2 , cs3 , cs5 cs1, cs4 data out high impedance valid data 90% 10% n ote: 1. mwr is high during read operation. timing measurement reference is 0.5 v dd . figure 1. read cycle timing diagram cdp1823, cdp1823c
5 dynamic electrical specifications at t a = -40 to +85 o c, v dd 5%, t r , t f = 20ns, c l = 100pf parameter symbol v dd (v) limits cdp1823 cdp1823c units (note 2) min (note 1) typ max (note 2) min (note 1) typ max write cycle (see figure 2) write recovery t wr 575- -75 - -ns 10 50 - - - - - ns write cycle t wc 5 400 - - 400 - - ns 10 225 - - - - - ns write pulse width t wrw 5 200 - - 200 - - ns 10 100 - - - - - ns address setup time t as 5 125 - - 125 - - ns 10 75 - - - - - ns data setup time t ds 5 100 - - 100 - - ns 10 75 - - - - - ns data hold time from mwr t dh 575- -75 - -ns 10 50 - - - - - ns notes: 1. typical values are at t a = 25 o c and nominal voltage. 2. time required by a limit device to allow for the indicated function. address t wc t as t wr cs1, cs4 cs2 , cs3 , cs5 t wrw t ds t dh mwr bus 0-7 valid data n ote: 1. mrd must be high during write operation. figure 2. write cycle timing diagram cdp1823, cdp1823c
6 data retention specifications at t a = -40 to +85 o c, see figure 3 parameter test conditions limits units cdp1823 cdp1823c v dr (v) v dd (v) min (note 1) typ max min (note 1) typ max minimum data retention voltage, v dr ---1.52-1.52v data retention quiescent current, i dd 2 - - 30 100 - 30 100 a chip deselect to data retention time - 5 600 - - 600 - - ns t cdr - 10300---- -ns recovery to normal operation time t rc - 5 600 - - 600 - - ns - 10300---- -ns v dd to v dr rise and fall time t r , t f 251--1-- s note: typical values are for t a = 25 o c and nominal v dd . figure 3. low v dd data retention timing waveforms figure 4. functional diagram 0.95 v dd v dd t cdr c s1 v ih v il t rc v ih v il 0.95 v dd v dr data retention mode t f t r ma0 buffer and decoder buffer control decoder 16 x 8 x 8 storage array ma1 ma2 ma3 ma4 ma5 ma6 mrd mwr cs1 cs3 cs2 cs4 cs5 bus 0-7 cdp1823, cdp1823c
7 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com figure 5. cdp1823 (128 x 8) minimum system (128 x 8) cpu/rom system ram interface address ma0 - ma7 tpa bus0 - bus7 mrd mwr ma0- ma7 tpa mrd ce0 bus0 - bus7 data cpu cdp1802 rom cdp1833 ram cdp1823 ma0 - ma6 mrd mwr cs bus0 - bus7 ram system cdp1823, cdp1823c
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